1. Field of the Invention
The present invention relates to an information processing device which is made up of a main data processing device (main processor) and a sub expansion processing device (coprocessor) for processing data according to instructions stored in a memory.
2. Description of the Related Art
In recent years, great improvements have been made in processing power by equipping data processing devices (hereinafter, "processors") with expansion computational devices (hereinafter, "coprocessors") which, according to necessity, execute special calculations at high speed.
The main conventional methods for providing such coprocessors consist of the installation of the coprocessor inside the main processor and of the connection of a coprocessor to the main processor according to necessity. Of these, the former installation method has the drawbacks of increases in cost and in power consumption when the coprocessor is not being used, so that a method for connecting a coprocessor which is equal in performance to an installed coprocessor is desired.
Conventional information processing devices which include a coprocessor connected to the main processor operate so that coprocessor calculations are performed by the processor decoding instructions for the coprocessor and then informing the coprocessor of the decoded commands. This method has a drawback in that the transfer of commands from the processor generates considerable overheads which makes the processing time taken by the coprocessor too long.
In response to this problem, Japanese Laid-Open Patent Application 1-240932 discloses an information processing device which, by having a coprocessor take and decode a same instruction at the same time as a processor which executes pipeline processing, can achieve a reduction in the time needed for command transfer and decoding.
However, when coprocessors in such conventional information processing devices execute processing using the data held in the general registers of the main processor, or when data processed by the coprocessor is stored in the general registers in the main processor, the data first has to be temporarily stored in the memory, with this transfer of data to the memory increasing execution time and thereby reducing the performance of the system.
Similarly, when coprocessors in such conventional information processing devices execute processing using the flag information held in the flag storage registers in the main processor or when flag information processed by the coprocessor is stored in the flag storage registers in the main processor, the flag information first has to be temporarily stored in the memory, with this transfer of flag information to the memory increasing execution time and thereby reducing the performance of the system.
Also, when data processed by the coprocessor and flag information processed by the coprocessor is stored in the flag storage registers and general registers in the main processor, it is necessary for the main processor to lock pipeline processing until the storage of the data and flag information in the general registers or flag storage registers is complete, which increases execution time and thereby reduces the performance of the system.
Similarly, when an interruption process arises during the processing of the coprocessor, since the data currently being processed cannot be stored, it becomes necessary for the coprocessor to reexecute the processing of the data after the interruption process has been completed. This increases execution time and thereby reduces the performance of the system.
Finally, when an task switching process arises during the processing of the coprocessor, since the data currently being processed cannot be stored, it becomes necessary for the coprocessor to reexecute the processing of the task process executed before task switching. This increases execution time and thereby reduces the performance of the system.